ASE Labs: News - Microsemi Collaborates with MathWorks to Deliver First Integrated FPGA-in-the-Loop Workflow for PolarFire and SmartFusion2 FPGA Development Boards

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style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0;text-align:left"><table class="spacer" style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><td height="16px" style="-moz-hyphens:auto;-webkit-hyphens:auto;Margin:0;border-collapse:collapse!important;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;hyphens:auto;line-height:16px;margin:0;mso-line-height-rule:exactly;padding:0;text-align:left;vertical-align:top;word-wrap:break-word"> </td></tr></tbody></table> <h4 class="text-center" style="-moz-hyphens:none;-webkit-hyphens:none;Margin:0;Margin-bottom:10px;color:#fff;font-family:Montserrat,Arial,sans-serif;font-size:18px;font-weight:400;hyphens:none;line-height:22px;margin:0;margin-bottom:10px;padding:0;text-align:center;text-transform:uppercase;word-break:none;word-wrap:normal">News From Microsemi Corporation</h4><h5 class="text-center" style="-moz-hyphens:none;-webkit-hyphens:none;Margin:0;Margin-bottom:10px;color:#fff;font-family:Montserrat,Arial,sans-serif;font-size:14px;font-weight:500;hyphens:none;line-height:18px;margin:0;margin-bottom:0;padding:0;text-align:center;word-break:none;word-wrap:normal">Transmitted by PR Newswire for Journalists on <span class="prevent-break" style="display:inline-block">April 19, 2018 06:00 AM EST </span></h5></th><th class="expander" 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style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0;text-align:left"> <table class="spacer" style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><td height="24px" style="-moz-hyphens:auto;-webkit-hyphens:auto;Margin:0;border-collapse:collapse!important;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:24px;font-weight:400;hyphens:auto;line-height:24px;margin:0;mso-line-height-rule:exactly;padding:0;text-align:left;vertical-align:top;word-wrap:break-word"> </td></tr></tbody></table> <h1 style="Margin:0;Margin-bottom:10px;color:#4D4E53;font-family:Montserrat,Arial,sans-serif;font-size:20px;font-weight:500;line-height:28px;margin:0;margin-bottom:0;padding:0;text-align:left;word-wrap:normal">Microsemi Collaborates with MathWorks to Deliver First Integrated FPGA-in-the-Loop Workflow for PolarFire and SmartFusion2 FPGA Development Boards</h1> <table class="spacer" style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><td height="24px" style="-moz-hyphens:auto;-webkit-hyphens:auto;Margin:0;border-collapse:collapse!important;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:24px;font-weight:400;hyphens:auto;line-height:24px;margin:0;mso-line-height-rule:exactly;padding:0;text-align:left;vertical-align:top;word-wrap:break-word"> </td></tr></tbody></table> </th><th class="expander" style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0!important;text-align:left;visibility:hidden;width:0"></th></tr></table></th> </tr></tbody></table> <table class="row content" style="background:#fff;border-collapse:collapse;border-spacing:0;display:table;padding:0;position:relative;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><th class="small-12 large-12 columns first last" style="Margin:0 auto;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0 auto;padding:0;padding-bottom:16px;padding-left:30px;padding-right:30px;text-align:left;width:570px"><table style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tr style="padding:0;text-align:left;vertical-align:top"><th style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0;text-align:left"> <table class="spacer" style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><td height="24px" style="-moz-hyphens:auto;-webkit-hyphens:auto;Margin:0;border-collapse:collapse!important;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:24px;font-weight:400;hyphens:auto;line-height:24px;margin:0;mso-line-height-rule:exactly;padding:0;text-align:left;vertical-align:top;word-wrap:break-word"> </td></tr></tbody></table><p class="sub-headline" style="Margin:0;Margin-bottom:10px;color:#4D4E53;font-family:Montserrat,Arial,sans-serif;font-size:14px;font-weight:500;line-height:20px;margin:0;margin-bottom:16px;padding:0;text-align:left"><strong>New Workflow Enables Customers to Automatically Generate Test Benches for HDL Verification</strong><p><span class="xn-location">ALISO VIEJO, Calif.</span>, <span class="xn-chron">April 19, 2018</span> /PRNewswire/ -- <b>Microsemi Corporation </b>(Nasdaq: MSCC), a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, today announced its collaboration with <a href="http://email.prnewswire.com/wf/click?upn=7VDqtAz2AW-2FeY7Xnbvsasab75t1-2B9nXVR6d-2FpGok98JY80ewlDIGjq0YkjPYcPUF4s3KmmidbPcNHE7uTDy6hjzSl8hcTS1ZdzicESwc6zvMzNa3HGcxVeFHpya-2Bv6661L1NvsCrieNaVQ-2FNGIqWQw-3D-3D_q1N77mbql2CxsoEfo2fFiZ6dnlev64IGUSa1KT1DDw1MuprZmQ6aap9NY9k0Le75xged1n4m9xzEvPpKRX1OWk474Cts3OazNl5vmhf5ckGtZSzJ9fc4gFb90-2B4s3rq7CcA-2Bc1LkByMTLpy8uLlnHKxxTM8enFR-2FblWse6DOeHokScvaO9pGEa2NRt73y6E8vpZVbaI6ojKy0brR7JLXJmEybdNU1WvVZ8G0n3dqeEwY4EgSrqAkv9lEj9v9aGnyJ1GOUCp7miCcTdkOVxzld1XN8RtJ1BesyynEKw6tGss3fph4ZzU1-2BBYXwv2pZYPvDKBuFnfcJYvTxwWrYHUBNg-3D-3D" rel="nofollow" target="_blank">MathWorks</a>Â®, a leading developer of mathematical computing software for engineers and scientists, to launch hardware support for field programmable gate array (FPGA)-in-the-loop (FIL) verification workflow with Microsemi <a href="http://email.prnewswire.com/wf/click?upn=7VDqtAz2AW-2FeY7Xnbvsasab75t1-2B9nXVR6d-2FpGok98KptG0anzRmHQjpZ-2BSefFatAq65PdUou2Q4IrYhOIIwnQ-3D-3D_q1N77mbql2CxsoEfo2fFiZ6dnlev64IGUSa1KT1DDw1MuprZmQ6aap9NY9k0Le75xged1n4m9xzEvPpKRX1OWk474Cts3OazNl5vmhf5ckGtZSzJ9fc4gFb90-2B4s3rq7CcA-2Bc1LkByMTLpy8uLlnHKxxTM8enFR-2FblWse6DOeHokScvaO9pGEa2NRt73y6E8HwpSBaJCyyT3bpdtWWzfiZVVh3WNofgxuY4ZxMGa9MDoR0XFPwZab-2FfMH6Frs8U5tlOQVFtRV9DtWHV4BVaUaNyviZhKoZSyGd2QYloJN4kl8Jj-2FrFdn27L-2BmiI8AajKFe0icV3FVr5z3-2FjWQzGzFw-3D-3D" rel="nofollow" target="_blank">FPGA</a> development boards. The new integrated FIL workflow with HDL Coderâ¢ and HDL Verifierâ¢ from MathWorks enables customers to automatically generate test benches for hardware description language (HDL) verification, including VHSIC Hardware Description Language (VHDL) and Verilog, providing rapid prototyping and verification of designs. </p>
<p>The collaboration with MathWorks enables customers to integrate  MATLABÂ®, a programming environment for algorithm development, data analysis, visualization and numeric computation, and SimulinkÂ®, a graphical environment for simulation and Model-Based Design, with Microsemi's <a href="http://email.prnewswire.com/wf/click?upn=7VDqtAz2AW-2FeY7Xnbvsasab75t1-2B9nXVR6d-2FpGok98J3lfPui7K3f3osUtYDV7zrO0jLvr4T3cnO5kNulxJeqxl5kVvaJh2GZ1Yy7v-2B72jOhbsCydIkmQ7qbftYDEzAoMimxOSwRCNeujc1TzGw5E7FXkWwyJYtyCXcEA-2B1r8bM-3D_q1N77mbql2CxsoEfo2fFiZ6dnlev64IGUSa1KT1DDw1MuprZmQ6aap9NY9k0Le75xged1n4m9xzEvPpKRX1OWk474Cts3OazNl5vmhf5ckGtZSzJ9fc4gFb90-2B4s3rq7CcA-2Bc1LkByMTLpy8uLlnHKxxTM8enFR-2FblWse6DOeHokScvaO9pGEa2NRt73y6E8XqKZHo-2BFVF151e069zErLUqr-2BM8pHA-2FHsOkDei9Le3W4xCpN5suESFoy0GDi1iymzyu-2ByGKEQOk8Vx6YMMrrshMjGCFsP-2FQ33G0wnkJ-2BEP2EO5BlRsSts3k5SSXctmVO-2BN-2Bum0LdX6N68n0tT2biAA-3D-3D" rel="nofollow" target="_blank">SmartFusionâ¢2 system-on-chip (SoC) FPGA</a> and <a href="http://email.prnewswire.com/wf/click?upn=7VDqtAz2AW-2FeY7Xnbvsasab75t1-2B9nXVR6d-2FpGok98J3lfPui7K3f3osUtYDV7zrO0jLvr4T3cnO5kNulxJeq2NTgOU3pv6gAWBVXJeu-2BdS1Mw3QuZEW1egyOt-2FhiBrah9lEenXGR1nJL-2BFMkMRg5A-3D-3D_q1N77mbql2CxsoEfo2fFiZ6dnlev64IGUSa1KT1DDw1MuprZmQ6aap9NY9k0Le75xged1n4m9xzEvPpKRX1OWk474Cts3OazNl5vmhf5ckGtZSzJ9fc4gFb90-2B4s3rq7CcA-2Bc1LkByMTLpy8uLlnHKxxTM8enFR-2FblWse6DOeHokScvaO9pGEa2NRt73y6E8pB6-2FBlqBJGvhi3dwdv2raprevXoNIGQM02oq8QzKNzhnERGBzBKj4Xs1GkG1hqQktumw2EdvNqXrtEITvqo-2F-2FA96hEeRO5aI-2Fsli05ipM4M9hHKJCZ1dVnyN3npz0tSezt0BXmoHlN5rJ6wEtd8Nuw-3D-3D" rel="nofollow" target="_blank">PolarFireÂ® FPGA</a> development boards, which allows the stimulation of designs through FIL verification workflow using Microsemi's development boards. FIL verification workflow enables customers to analyze the results back in MATLAB and Simulink. </p><th class="expander" style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0!important;text-align:left;visibility:hidden;width:0"></th></tr></table></th></tr></tbody></table><table class="row content" style="background:#fff;border-collapse:collapse;border-spacing:0;display:table;padding:0;position:relative;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><th class="small-12 large-12 columns first last" style="Margin:0 auto;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0 auto;padding:0;padding-bottom:16px;padding-left:30px;padding-right:30px;text-align:left;width:570px"><table style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tr style="padding:0;text-align:left;vertical-align:top"><th style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0;text-align:left"><center data-parsed="" style="min-width:510px;width:100%"><img src="https://mma.prnewswire.com/media/678925/Microsemi_Corporation_Collaborates_with_MathWorks.jpg" alt="" align="center" class="float-center" style="-ms-interpolation-mode:bicubic;Margin:0 auto;clear:both;display:block;float:none;margin:0 auto;max-width:100%;outline:0;text-align:center;text-decoration:none;width:auto"></center></th><th class="expander" style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0!important;text-align:left;visibility:hidden;width:0"></th></tr></table></th></tr></tbody></table><table class="row content" style="background:#fff;border-collapse:collapse;border-spacing:0;display:table;padding:0;position:relative;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><th class="small-12 large-12 columns first last" style="Margin:0 auto;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0 auto;padding:0;padding-bottom:16px;padding-left:30px;padding-right:30px;text-align:left;width:570px"><table style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tr style="padding:0;text-align:left;vertical-align:top"><th style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0;text-align:left">
<p>"With the ever-increasing complexity in algorithm designs, it has become imperative for designers to quickly design and validate their algorithms on real hardware," said <span class="xn-person">Shakeel Peera</span>, vice president FPGA marketing for Microsemi. "This integrated FPGA-in-the-loop workflow of Microsemi FPGA boards with MathWorks HDL Verifier will allow system engineers and algorithm developers to quickly prototype and implement their MATLAB and Simulink designs on Microsemi FPGA development boards through our <a href="http://email.prnewswire.com/wf/click?upn=7VDqtAz2AW-2FeY7Xnbvsasab75t1-2B9nXVR6d-2FpGok98J3lfPui7K3f3osUtYDV7zrO0jLvr4T3cnO5kNulxJeqx6qMgM1uQwP10KgvXS-2BzhsUccxYtFAuKH3zthzbOIWU_q1N77mbql2CxsoEfo2fFiZ6dnlev64IGUSa1KT1DDw1MuprZmQ6aap9NY9k0Le75xged1n4m9xzEvPpKRX1OWk474Cts3OazNl5vmhf5ckGtZSzJ9fc4gFb90-2B4s3rq7CcA-2Bc1LkByMTLpy8uLlnHKxxTM8enFR-2FblWse6DOeHokScvaO9pGEa2NRt73y6E8ysxYQ6z1sas6-2FMHdVx4uYvQrQ5N-2BHyhnNFUYJlqDOi1d1bLfouH1hupszp6TMSBS07rSQi3oYZR-2FalhEjj8ryqNqOCp1YayzDspUrsdz6QziMY4OW7LrqB9VqlVPR-2BUDSvV4aAOH67DVJYoLCK9ZmA-3D-3D" rel="nofollow" target="_blank">Libero SoC Design Suite</a>."</p>
<p>Microsemi's collaboration with MathWorks enables a unified workflow to verify designs comprehensively. It integrates Microsemi's Libero SoC Design Suiteâa comprehensive, easy to learn, easy to adopt development toolset for designing with Microsemi's FPGAs and SoC FPGAsâwith MATLAB and Simulink for design verification, and provides FIL verification with Microsemi FPGA boards. This allows customers to catch bugs early in the design cycle, helping reduce time to market and enabling early verification.</p>
<p>"MATLAB and Simulink are widely used by engineers to develop algorithms targeting FPGAs," said <span class="xn-person">Paul Barnard</span>, director of marketing for the Simulink product family at MathWorks. "Now that HDL Verifier supports FIL for Microsemi development kits, engineers can connect designs implemented on these FPGA boards directly to MATLAB and Simulink test benches, streamlining a crucial validation step in developing safety-critical avionics, space and other applications." </p>
<p>Delivering the industry's first FIL feature for Microsemi boards with MATLAB and Simulink, the collaboration provides HDL Verifier Support Package for Microsemi FPGA, a hardware support package for SmartFusion2 SoC FPGA and PolarFire FPGA development boards, and an integrated workflow from algorithms to implementation. Leveraging HDL Verifer, enabled by Microsemi's Accelerate Ecosystem, makes Microsemi's FPGAs ideal for a wide variety of applications within the <a href="http://email.prnewswire.com/wf/click?upn=TwIh0OIjG8BOSB67uKqqj1l6zmnQdlEJOUQfo-2BFvQ2LzBaVcl6xbiQwHmgJKC6ktN4QQdy-2F9V7FG9dztfmE7NQ-3D-3D_q1N77mbql2CxsoEfo2fFiZ6dnlev64IGUSa1KT1DDw1MuprZmQ6aap9NY9k0Le75xged1n4m9xzEvPpKRX1OWk474Cts3OazNl5vmhf5ckGtZSzJ9fc4gFb90-2B4s3rq7CcA-2Bc1LkByMTLpy8uLlnHKxxTM8enFR-2FblWse6DOeHokScvaO9pGEa2NRt73y6E8QSmjgmYkEgcQND8hDg2pArKur3jk4H9Ku7MSHANjPF9UViBgz9WMsXDWbCrdbJoRIf-2F0EFWvjVQVnJ0PSafEcewyv1f2RMWJeKD4YYPq-2FPTLYFOiA7L3fNLaXUUwWhs2TsLI8AXacQTJvk0Go3pSCA-3D-3D" rel="nofollow" target="_blank">aerospace</a> and <a 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href="http://email.prnewswire.com/wf/click?upn=TwIh0OIjG8BOSB67uKqqj1l6zmnQdlEJOUQfo-2BFvQ2JGKFVUU3lm95nWCKwVF2u71EYnif5vGe0p3-2FQNGlyujw-3D-3D_q1N77mbql2CxsoEfo2fFiZ6dnlev64IGUSa1KT1DDw1MuprZmQ6aap9NY9k0Le75xged1n4m9xzEvPpKRX1OWk474Cts3OazNl5vmhf5ckGtZSzJ9fc4gFb90-2B4s3rq7CcA-2Bc1LkByMTLpy8uLlnHKxxTM8enFR-2FblWse6DOeHokScvaO9pGEa2NRt73y6E82nf0q1HEpROFMwtZLgy-2FNSzerrdLoT7JtBlWhYnsGk4mlKrSEjilRD86pTMDkg6GhX5CGhclvsKWn-2FjRbFRRn5x6Di8e4znP5z-2BPzShPra-2FHu98LNq-2Bm9Br1cn-2B6gyJlTEt7wUmfEsalKDG9-2FHmUng-3D-3D" rel="nofollow" target="_blank">digital signal processing</a>, <a href="http://email.prnewswire.com/wf/click?upn=TwIh0OIjG8BOSB67uKqqj1l6zmnQdlEJOUQfo-2BFvQ2Lk5NPmfo9C0iLpcQJ21S17F8zyurSkghmb9QR0tUhLlw-3D-3D_q1N77mbql2CxsoEfo2fFiZ6dnlev64IGUSa1KT1DDw1MuprZmQ6aap9NY9k0Le75xged1n4m9xzEvPpKRX1OWk474Cts3OazNl5vmhf5ckGtZSzJ9fc4gFb90-2B4s3rq7CcA-2Bc1LkByMTLpy8uLlnHKxxTM8enFR-2FblWse6DOeHokScvaO9pGEa2NRt73y6E8cean-2BQiAmpG6Rr4hi7UDg6LieW6zWZyf-2FOX-2BJiXB5ASWrylBUXVuwP2Z2zk3rGnnc1DfoMwd5hqKGNYCjwSkQEVoe40lPDuStXPyK88ksveKHebzFwiDG0X4Zs3Ygl78lJR8qYXldXu5Hq78CyWLrA-3D-3D" rel="nofollow" target="_blank">communication systems</a>, <a href="http://email.prnewswire.com/wf/click?upn=7VDqtAz2AW-2FeY7Xnbvsasab75t1-2B9nXVR6d-2FpGok98KzlkLkglTvQSyYJmJKAvP5-2Fxj2xsChrxvqlQcOkuM26b6ik3pyqLf2wjMXtipy06k-3D_q1N77mbql2CxsoEfo2fFiZ6dnlev64IGUSa1KT1DDw1MuprZmQ6aap9NY9k0Le75xged1n4m9xzEvPpKRX1OWk474Cts3OazNl5vmhf5ckGtZSzJ9fc4gFb90-2B4s3rq7CcA-2Bc1LkByMTLpy8uLlnHKxxTM8enFR-2FblWse6DOeHokScvaO9pGEa2NRt73y6E8Hwvx1ATGgdgyxEyRZo8zWvic1zKqErx7wriB-2FjdG1WJwmovRxk1Y79Sgxf7NhT-2BtgVrZV-2FoaZoQl-2FlMrrsVc6Hii7rFdRgmnzRw7v6LzcaXWu7W5gr3NeD7W0iGAuOyRBbFjkL3QQxJqzbrYuOmHRw-3D-3D" rel="nofollow" target="_blank">machine vision</a> and <a href="http://email.prnewswire.com/wf/click?upn=TwIh0OIjG8BOSB67uKqqj1l6zmnQdlEJOUQfo-2BFvQ2JGKFVUU3lm95nWCKwVF2u7AsG1JSyad-2FKEyEX2oxWgzw-3D-3D_q1N77mbql2CxsoEfo2fFiZ6dnlev64IGUSa1KT1DDw1MuprZmQ6aap9NY9k0Le75xged1n4m9xzEvPpKRX1OWk474Cts3OazNl5vmhf5ckGtZSzJ9fc4gFb90-2B4s3rq7CcA-2Bc1LkByMTLpy8uLlnHKxxTM8enFR-2FblWse6DOeHokScvaO9pGEa2NRt73y6E8bZ5z5oYOfs-2Bhh63nzAKjnafLAtYOqSIvr3AMhG2ko-2Bvya2FcVGAEWJKExL7PqsX5UFNEWkWg28abDp5qK8tOY2U4cQlouEheYr-2BG3kNXhyO3GVXNLqVaN0ATGNZmZ0BSyWophItQak2jiWXF4iwIPg-3D-3D" rel="nofollow" target="_blank">imaging systems</a>, control systems, <a href="http://email.prnewswire.com/wf/click?upn=7VDqtAz2AW-2FeY7Xnbvsasab75t1-2B9nXVR6d-2FpGok98JQGC85Oj0rBwUlD2nVp-2BABSgugvHcZpk1Q6PbX49WagE6oigYTm40Rc-2BqzeEboy8XtU1YOC6kk-2FygTDeAhnd5R_q1N77mbql2CxsoEfo2fFiZ6dnlev64IGUSa1KT1DDw1MuprZmQ6aap9NY9k0Le75xged1n4m9xzEvPpKRX1OWk474Cts3OazNl5vmhf5ckGtZSzJ9fc4gFb90-2B4s3rq7CcA-2Bc1LkByMTLpy8uLlnHKxxTM8enFR-2FblWse6DOeHokScvaO9pGEa2NRt73y6E8j1eJmiW-2B89Jc9OclPnHql9lDqTbkLE6zVKFFvUJhtcniiIaWPil0RcBhtDaIdYQaQgB40Vq6K1W5-2FmAh-2FjJz7aNiFHK-2F4kT4sbBBWpVKe2qevNWpXEaIUZnehOnRbfBqEACu6Cw-2Fc6ELeuC6AAhD4g-3D-3D" rel="nofollow" target="_blank">military communications</a>, and <a href="http://email.prnewswire.com/wf/click?upn=TwIh0OIjG8BOSB67uKqqj1l6zmnQdlEJOUQfo-2BFvQ2IYv-2BP6mPrTgDH5x8oFtNRwqdGogiCWYzNdcNBlhHGdWAfjfRuhgUEFsEdMYGhL8pI-3D_q1N77mbql2CxsoEfo2fFiZ6dnlev64IGUSa1KT1DDw1MuprZmQ6aap9NY9k0Le75xged1n4m9xzEvPpKRX1OWk474Cts3OazNl5vmhf5ckGtZSzJ9fc4gFb90-2B4s3rq7CcA-2Bc1LkByMTLpy8uLlnHKxxTM8enFR-2FblWse6DOeHokScvaO9pGEa2NRt73y6E8aUuL9CsXrNd-2FMgZElVDM1aamcA10MfWrk8vRrtbDkaJViES4I-2Fcet8xXKAlNxYNrhQPGJrOoeTM0iEM1UkHWm6Yxy0Rw16VZs5M40K4j50cLB0PsgRLLvpkc9mY88owJd8brvcmcB7gXUBWC6hNkQQ-3D-3D" rel="nofollow" target="_blank">payload</a> and radio processing.</p>
<p>The usage of FPGA verification significantly reduces timelines and development costs and has experienced considerable adoption in defense, automotive and industrial markets, leading to a booming <span class="xn-money">$68 million</span> for FPGA verification since <span class="xn-chron">September 2017</span> (as of <span class="xn-chron">March 2018</span>), growing at a compound annual growth rate (CAGR) of nearly 8 percent through 2025 according to IndustryARC. The market research firm also notes FPGA verification has an untapped potential market (total addressable market, or TAM) of <span class="xn-money">$425 million</span> with a tapped service addressable market (SAM) of <span class="xn-money">$141 million</span>. </p>
<p><b>About Microsemi's Accelerate Ecosystem<br></b>Microsemi's Accelerate Ecosystem facilitates collaboration between Microsemi and leading firms in the semiconductor integrated circuit (IC), IP, systems, software, tools and design spaces to integrate, test and deliver pre-validated designs and system-level solutions for end customers in Microsemi's key vertical marketsâaerospace and defense, data center, communications and industrial. The Accelerate Ecosystem is designed to reduce time-to-market for end customers and time-to-revenue for Microsemi and ecosystem members via technology alignment, joint marketing and sales acceleration. Learn more at <a href="http://email.prnewswire.com/wf/click?upn=7VDqtAz2AW-2FeY7Xnbvsasab75t1-2B9nXVR6d-2FpGok98KptG0anzRmHQjpZ-2BSefFativ7xu6urzuqNxEntBN9JIw-3D-3D_q1N77mbql2CxsoEfo2fFiZ6dnlev64IGUSa1KT1DDw1MuprZmQ6aap9NY9k0Le75xged1n4m9xzEvPpKRX1OWk474Cts3OazNl5vmhf5ckGtZSzJ9fc4gFb90-2B4s3rq7CcA-2Bc1LkByMTLpy8uLlnHKxxTM8enFR-2FblWse6DOeHokScvaO9pGEa2NRt73y6E8E0EBdKoDjf1eVozOGb2t6j4oYHOS0EbMLSWDxJKbw4SjqeZaejJBBel9OVVs-2BwAkHABwbBeNBsFGlXjjiNC-2FM2tQK-2F0vfAzDHO3rNKHzRriT3EXwgzEY3OkqggctBmI-2BSSQTrX9okiTmlN0-2BBEIm5w-3D-3D" rel="nofollow" target="_blank">https://www.microsemi.com/product-directory/4194-partners</a>. </p>
<p><b>Product Availability<br></b>Microsemi's <a href="http://email.prnewswire.com/wf/click?upn=7VDqtAz2AW-2FeY7Xnbvsasab75t1-2B9nXVR6d-2FpGok98J3lfPui7K3f3osUtYDV7zrn96FFb8cXKyZz8hw-2BneWULFI2-2FtJM7-2BvtO8lKoiczNE-3D_q1N77mbql2CxsoEfo2fFiZ6dnlev64IGUSa1KT1DDw1MuprZmQ6aap9NY9k0Le75xged1n4m9xzEvPpKRX1OWk474Cts3OazNl5vmhf5ckGtZSzJ9fc4gFb90-2B4s3rq7CcA-2Bc1LkByMTLpy8uLlnHKxxTM8enFR-2FblWse6DOeHokScvaO9pGEa2NRt73y6E8Wq-2Fk1coyn2PUOaYDtudaf2Wp7Vw9CfExdFclr3N8Ym6wwF7eH5-2BrZYC5sriYFFOthmay94u39osy519BJdKi2DQEs5af3U103g4-2F8BaZkj6pAq4D5Zy-2BhUkzNcosd54kraddvFIpsPZaOEbe8zfsjQ-3D-3D" rel="nofollow" target="_blank">SmartFusion2</a> and <a href="http://email.prnewswire.com/wf/click?upn=7VDqtAz2AW-2FeY7Xnbvsasab75t1-2B9nXVR6d-2FpGok98J3lfPui7K3f3osUtYDV7zr0BKvK2tZTlVygBP3rMCYOuqAWlyHUSHia3LZzhcIqLY-3D_q1N77mbql2CxsoEfo2fFiZ6dnlev64IGUSa1KT1DDw1MuprZmQ6aap9NY9k0Le75xged1n4m9xzEvPpKRX1OWk474Cts3OazNl5vmhf5ckGtZSzJ9fc4gFb90-2B4s3rq7CcA-2Bc1LkByMTLpy8uLlnHKxxTM8enFR-2FblWse6DOeHokScvaO9pGEa2NRt73y6E81k053n60gFJZqiqmy9Ujp9OIUmp1alCMbMjnv-2F5x2y5v8J-2BZ7ixzGESR7WQ-2F6jsMcdXAMNWg6AEimP0kPfil8ZsT47EZiqTLyvXnhuK0kA1qD6lBmLB9YHawiX-2BO9E3atjrbgfwnT5CpZhtR-2B1VMSg-3D-3D" rel="nofollow" target="_blank">PolarFire</a> FPGAs, and their complementary development boards, are available now, and MathWorks' HDL Coder and HDL Verifier are also available now. For more information, visit <a href="http://email.prnewswire.com/wf/click?upn=TwIh0OIjG8BOSB67uKqqj1l6zmnQdlEJOUQfo-2BFvQ2JGKFVUU3lm95nWCKwVF2u7EdI40CYsSGi0x-2BVh7QyMjA-3D-3D_q1N77mbql2CxsoEfo2fFiZ6dnlev64IGUSa1KT1DDw1MuprZmQ6aap9NY9k0Le75xged1n4m9xzEvPpKRX1OWk474Cts3OazNl5vmhf5ckGtZSzJ9fc4gFb90-2B4s3rq7CcA-2Bc1LkByMTLpy8uLlnHKxxTM8enFR-2FblWse6DOeHokScvaO9pGEa2NRt73y6E8GaiiSi0UrXShyJIFzAZJopodoJHbUpzF82BkgSbMTrAM-2Fx2LC8a3NnBFTQcFsZSZhGiFexPDzG15icz4jbSrfiALaQvw8oiuUZw2rjmTp3frrnppMMeYT9-2FEQoXFDz2YhNBK9K5DRnGQfYSVag3Ihw-3D-3D" rel="nofollow" target="_blank">http://www.microsemi.com/products/fpga-soc/fpgas</a> and <a href="http://email.prnewswire.com/wf/click?upn=7VDqtAz2AW-2FeY7XnbvsasYiHIAsHwkqE2R7Ngcl0-2FglKoVp7fk9D4nFbeenK2Mnui4w6YX1Xe7fHqj0DwX8fGA-3D-3D_q1N77mbql2CxsoEfo2fFiZ6dnlev64IGUSa1KT1DDw1MuprZmQ6aap9NY9k0Le75xged1n4m9xzEvPpKRX1OWk474Cts3OazNl5vmhf5ckGtZSzJ9fc4gFb90-2B4s3rq7CcA-2Bc1LkByMTLpy8uLlnHKxxTM8enFR-2FblWse6DOeHokScvaO9pGEa2NRt73y6E8LCGF4wdGQoZMVQEw-2BuGSYGhdNdMwqmUrFNJ2oiBTph4UYQXuaOtx8TpdC2Y0DAE4bv1ZkKSquEc9HJu5iF7Y68gzg7eRRWj5eYn4PuibbalKpHcIPybOw8S1xkht4y75gee5orXAROoiNGY6aNdiWQ-3D-3D" rel="nofollow" target="_blank">https://www.mathworks.com/products/hdl-verifier.html</a>, respectively, or contact <a href="mailto:sales.support@microsemi.com" rel="nofollow" target="_blank">sales.support@microsemi.com</a>. </p>
<p><b>About Microsemi's FPGAs<br></b>Microsemi's new cost-optimized <a href="http://email.prnewswire.com/wf/click?upn=TwIh0OIjG8BOSB67uKqqj1l6zmnQdlEJOUQfo-2BFvQ2LYizMDQCDhjlAFnPYxFDvI_q1N77mbql2CxsoEfo2fFiZ6dnlev64IGUSa1KT1DDw1MuprZmQ6aap9NY9k0Le75xged1n4m9xzEvPpKRX1OWk474Cts3OazNl5vmhf5ckGtZSzJ9fc4gFb90-2B4s3rq7CcA-2Bc1LkByMTLpy8uLlnHKxxTM8enFR-2FblWse6DOeHokScvaO9pGEa2NRt73y6E8l6CDezdYvoAMNhZ9I9tx1om1B6oF1fweb-2FVKLzV9tDNRVy455WDGfmQoT0flPx-2Fef4Vm006AM5eBoFvCoG2Q-2B8Yqk6yMP-2FQU8Er0A29pisAVsRKRnTWaXyZhPRTDJ-2BGtkH2pPcg-2Bk524AfT-2FFdOFJQ-3D-3D" rel="nofollow" target="_blank">PolarFire FPGAs</a> deliver the industry's lowest power at mid-range densities with exceptional security and reliability. The product family features 12.7 Gbps SerDes transceivers at up to 50 percent lower power than competing FPGAs. With densities spanning from <span class="xn-money">100K</span> to <span class="xn-money">500K</span> logic elements (LEs), the non-volatile PolarFire product family consumes 10 times less static power than competitive devices and features an even lower standby power referred to as Flash*Freeze. The company's <a href="http://email.prnewswire.com/wf/click?upn=TwIh0OIjG8BOSB67uKqqj1l6zmnQdlEJOUQfo-2BFvQ2JGKFVUU3lm95nWCKwVF2u71znIpqZk5AtOIbfchKMh-2Fgf4Nti3z1OFj0e0Eu6njlQ-3D_q1N77mbql2CxsoEfo2fFiZ6dnlev64IGUSa1KT1DDw1MuprZmQ6aap9NY9k0Le75xged1n4m9xzEvPpKRX1OWk474Cts3OazNl5vmhf5ckGtZSzJ9fc4gFb90-2B4s3rq7CcA-2Bc1LkByMTLpy8uLlnHKxxTM8enFR-2FblWse6DOeHokScvaO9pGEa2NRt73y6E8NTJEnSFJEJFVXLKgtg2-2BwMKg6ucLopiS8M1-2F-2FEAidGxv7Xo88jFcdsYH8iH1ZsXSZ6ZOdbQ5IuKbYPNJPZ67awgo4r6lGLcQJXVdvY5VRIvLc7ugW6sfB5qBJzC0musN6ZsYOX24NdrA26r4Ohqu-2FA-3D-3D" rel="nofollow" target="_blank">IGLOOâ¢2 FPGAs</a> and <a href="http://email.prnewswire.com/wf/click?upn=TwIh0OIjG8BOSB67uKqqj1l6zmnQdlEJOUQfo-2BFvQ2JGKFVUU3lm95nWCKwVF2u7CMIverPABSz13w0WEHdEJwo4ajr8yCuHbjKTMW1DEy0-3D_q1N77mbql2CxsoEfo2fFiZ6dnlev64IGUSa1KT1DDw1MuprZmQ6aap9NY9k0Le75xged1n4m9xzEvPpKRX1OWk474Cts3OazNl5vmhf5ckGtZSzJ9fc4gFb90-2B4s3rq7CcA-2Bc1LkByMTLpy8uLlnHKxxTM8enFR-2FblWse6DOeHokScvaO9pGEa2NRt73y6E8l3mLuPm6DRNuekD1ICgNnQQEZMF10K7FiaLCDiSHUlroS9lekpLA2A00-2FfhNtUOaCyQVx6-2BxsoBjgrnl7Kd0-2F1Z-2B08hq93M9O7buyx4-2FJiSUEV97KU2Qtc47XkYwVwlSN9kY2Z5A9qniAvtHQylJ6A-3D-3D" rel="nofollow" target="_blank">SmartFusion2 SoC FPGAs</a> deliver more resources in low density devices, with the lowest power, proven security and exceptional reliability. The devices offer 30-50 percent more power efficiency and are ideal for general purpose functions such as Gigabit Ethernet or dual PCI Express control planes, bridging functions, input/output (I/O) expansion and conversion, video/image processing, system management and secure connectivity. Microsemi's <a href="http://email.prnewswire.com/wf/click?upn=TwIh0OIjG8BOSB67uKqqj1l6zmnQdlEJOUQfo-2BFvQ2JGKFVUU3lm95nWCKwVF2u7z3yV4OanQ1ZWU4GNEIIDE-2FKwxoBHuVdz4ww5xaSYsEE-3D_q1N77mbql2CxsoEfo2fFiZ6dnlev64IGUSa1KT1DDw1MuprZmQ6aap9NY9k0Le75xged1n4m9xzEvPpKRX1OWk474Cts3OazNl5vmhf5ckGtZSzJ9fc4gFb90-2B4s3rq7CcA-2Bc1LkByMTLpy8uLlnHKxxTM8enFR-2FblWse6DOeHokScvaO9pGEa2NRt73y6E87u-2BgAh3-2FUG1-2FW4EWgncBB1K0OIJP8WHdC1g8AdcU8imryVOh-2FdfVw6S67AGaKpWbokg8lJwhAvC6r8zJ7T-2ByKEijAhen2rrxsKIBYfycxvPCwzUYolyVK38xPzBPXYBl8RdV0P3t-2FFD6ojK8qJlzfg-3D-3D" rel="nofollow" target="_blank">RTG4 FPGAs</a> bring new capabilities to the market and combine a wealth of features with the highest quality and reliability to meet the increasing demands of modern satellite payloads. RTG4's reprogrammable flash technology offers complete immunity to radiation-induced configuration upsets in the harshest radiation environments, without the configuration scrubbing required with SRAM FPGA technology. </p>
<p><b>About Microsemi<br></b>Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; enterprise storage and communication solutions, security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in <span class="xn-location">Aliso Viejo, California</span> and has approximately 4,800 employees globally. Learn more at <a href="http://email.prnewswire.com/wf/click?upn=TwIh0OIjG8BOSB67uKqqj1l6zmnQdlEJOUQfo-2BFvQ2I-3D_q1N77mbql2CxsoEfo2fFiZ6dnlev64IGUSa1KT1DDw1MuprZmQ6aap9NY9k0Le75xged1n4m9xzEvPpKRX1OWk474Cts3OazNl5vmhf5ckGtZSzJ9fc4gFb90-2B4s3rq7CcA-2Bc1LkByMTLpy8uLlnHKxxTM8enFR-2FblWse6DOeHokScvaO9pGEa2NRt73y6E8l4ZP-2BqbrHrxryMs-2BlKg-2B2uqFnaurs3K6t7FJCvTtKg5F0EXI6HLYZvLuRNq1OC-2BI7gqoC5ZhYIU8Y3MqcQTpG6Le2mxr8o7HxRZuXi0gq5goe8yiC9HQNX-2BJXi4KLxQsO4Fvvs7RjJqZ6ToqRAfPsA-3D-3D" rel="nofollow" target="_blank">http://www.microsemi.com</a>. </p>
<p>Microsemi and the Microsemi logo are registered trademarks or service marks of Microsemi Corporation and/or its affiliates. Third-party trademarks and service marks mentioned herein are the property of their respective owners.</p>
<p>"Safe Harbor" Statement under the Private Securities Litigation Reform Act of 1995: Any statements set forth in this news release that are not entirely historical and factual in nature, including statements related to its collaboration with MathWorks, a leading developer of mathematical computing software for engineers and scientists, to launch hardware support for field programmable gate array (FPGA)-in-the-loop (FIL) workflow with Microsemi development boards, and its potential effects on future business, are forward-looking statements. These forward-looking statements are based on our current expectations and are inherently subject to risks and uncertainties that could cause actual results to differ materially from those expressed in the forward-looking statements. The potential risks and uncertainties include, but are not limited to, such factors as rapidly changing technology and product obsolescence, potential cost increases, variations in customer order preferences, weakness or competitive pricing environment of the marketplace, uncertain demand for and acceptance of the company's products, adverse circumstances in any of our end markets, results of in-process or planned development or marketing and promotional campaigns, difficulties foreseeing future demand, potential non-realization of expected orders or non-realization of backlog, product returns, product liability, and other potential unexpected business and economic conditions or adverse changes in current or expected industry conditions, difficulties and costs of protecting patents and other proprietary rights, inventory obsolescence and difficulties regarding customer qualification of products. In addition to these factors and any other factors mentioned elsewhere in this news release, the reader should refer as well to the factors, uncertainties or risks identified in the company's most recent Form 10-K and all subsequent Form 10-Q reports filed by Microsemi with the SEC. Additional risk factors may be identified from time to time in Microsemi's future filings. The forward-looking statements included in this release speak only as of the date hereof, and Microsemi does not undertake any obligation to update these forward-looking statements to reflect subsequent events or circumstances.</p>
<p> </p>

<p>SOURCE Microsemi Corporation</p><th class="expander" style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0!important;text-align:left;visibility:hidden;width:0"></th></tr></table></th></tr></tbody></table><table class="row content" style="background:#fff;border-collapse:collapse;border-spacing:0;display:table;padding:0;position:relative;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><th class="gallery small-12 large-12 columns first last" style="Margin:0 auto;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0 auto;padding:0;padding-bottom:16px;padding-left:30px;padding-right:30px;text-align:left;width:570px"><table style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tr style="padding:0;text-align:left;vertical-align:top"><th style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0;text-align:left"><table class="row" style="border-collapse:collapse;border-spacing:0;display:table;padding:0;position:relative;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><th class="small-12 large-12 columns first last" style="Margin:0 auto;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0 auto;padding:0;padding-bottom:16px;padding-left:0!important;padding-right:0!important;text-align:left;width:100%"><table style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tr style="padding:0;text-align:left;vertical-align:top"><th style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0;text-align:left"><center data-parsed="" style="min-width:none!important;width:100%"><img src="https://mma.prnewswire.com/media/74808/microsemi_corporation_logo.jpg" alt="" align="center" class="float-center" style="-ms-interpolation-mode:bicubic;Margin:0 auto;clear:both;display:block;float:none;margin:0 auto;max-width:100%;outline:0;text-align:center;text-decoration:none;width:auto"></center><table class="spacer" style="border-collapse:collapse;border-spacing:0;padding:0;text-align:left;vertical-align:top;width:100%"><tbody><tr style="padding:0;text-align:left;vertical-align:top"><td height="16px" style="-moz-hyphens:auto;-webkit-hyphens:auto;Margin:0;border-collapse:collapse!important;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;hyphens:auto;line-height:16px;margin:0;mso-line-height-rule:exactly;padding:0;text-align:left;vertical-align:top;word-wrap:break-word"> </td></tr></tbody></table><p style="Margin:0;Margin-bottom:10px;color:#4D4E53;font-family:Montserrat,Arial,sans-serif;font-size:14px;font-weight:400;line-height:28px;margin:0;margin-bottom:16px;padding:0;text-align:left">Microsemi Corporation. (PRNewsFoto/Microsemi Corporation)</p><hr style="border:1px solid #8a8a8d;border-bottom:0"></th><th class="expander" style="Margin:0;color:#0a0a0a;font-family:Montserrat,Arial,sans-serif;font-size:16px;font-weight:400;line-height:1.3;margin:0;padding:0!important;text-align:left;visibility:hidden;width:0"></th></tr></table></th></tr></tbody></table>CONTACT: Beth P. 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Microsemi Collaborates with MathWorks to Deliver First Integrated FPGA-in-the-Loop Workflow for PolarFire and SmartFusion2 FPGA Development Boards

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